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Hi there, I'm

Abhinav Datta

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ECE Student passionate about technology and problem solving. Building both hardware and software solutions.

About Me

I'm Abhinav Datta — an ECE student passionate about technology and problem solving. I enjoy working across the stack, from embedded systems to web development, and I'm always exploring new technologies.

77
Repos
6+
Languages
ECE
Core

Recent GitHub Activity

Abhinav's Github Chart
GitHub Stats Top Languages

Experience

Software Engineering Intern

May 2026 – Present

Uptricks Services Pvt. Ltd. • Pune, India (Remote)

  • Improved module reliability by debugging logic errors across 3 active feature modules, reducing reported defects by 20% within the first month.
  • Strengthened code quality by implementing structured validation checks, ensuring 100% of assigned modules met functional specifications before release.
  • Applied systematic problem-solving to identify root causes of application failures, demonstrating debugging discipline transferable to hardware verification workflows.
DebuggingTestingSoftware DevelopmentProblem Solving

IoT & Embedded Systems Intern

Apr 2026 – May 2026

Upskill Campus / UniConverge Technologies • Vijayawada, India

  • Designed and implemented a Smart Industrial Monitoring System using ESP8266 NodeMCU, DHT11, and MQ-2 sensors to track temperature, humidity, and gas levels in real time.
  • Integrated sensor data with the Blynk Cloud platform, enabling remote dashboards and instant alerts when abnormal conditions were detected.
  • Validated system performance through structured test cases, achieving stable Wi-Fi connectivity and under 2s alert response time across all monitored parameters.
  • Documented a modular design flow supporting easy integration of additional sensors and IoT protocols (MQTT, HTTP).
ESP8266IoTMQTTEmbedded SystemsBlynk

Content Writer Intern

Apr 2026 • 2 weeks

InAmigos Foundation (IAF) • Remote

Delivered all assigned articles ahead of deadline, demonstrating strong time management and technical writing skills.

Technical WritingContent CreationCommunication

Digital Design & Verification Intern

Jan 2025 – Mar 2025

EdiGlobe • Vijayawada, India (Remote)

  • Accelerated simulation debug cycles by 30% by developing structured SystemVerilog testbenches to verify combinational and sequential logic across 3 digital circuit designs.
  • Improved functional verification coverage to 90%+ by applying constrained-random stimulus techniques to validate logic gate behaviour against defined functional specifications.
  • Reduced simulation error rate by 25% by systematically troubleshooting Verilog HDL models through waveform analysis, resolving timing and logic faults across all project milestones.
  • Delivered all verification tasks 100% on schedule by following a structured test plan aligned with standard VLSI design verification flows.
SystemVerilogVerilogVLSIVerificationUVM

Tech Stack

Languages

CC++PythonJavaScriptHTMLCSSSystemVerilogVerilog HDL

Tools & Platforms

GitGitHubVS CodeLinuxAndroid StudioMATLAB

Domains

Embedded SystemsWeb DevelopmentDigital ElectronicsVLSI VerificationIoTAI & Modern Tech

Proficiency

Python80%
C / C++70%
SystemVerilog / Verilog65%
JavaScript / Web60%
Embedded C / IoT65%

Featured Projects

Recent GitHub Activity

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Get in Touch

Feel free to reach out for collaborations, opportunities, or just a chat.